`timescale 10ns/1ps

module SingleCycleProcessor_test;

	reg Clk, RESET;
	wire [7:0] M0, M1, M5, M16, M17; //for test
	
	SingleCycleProcessor U0(.*);

	initial
	begin
		Clk=1'b0;
		forever #0.5 Clk=~Clk;
	end

	initial
	fork
		RESET<=1'b1;
		#1 RESET <=1'b0;
	join
endmodule